1. Field of the Invention
The present invention relates to the manufacture of high performance VLSI semiconductor chips in general and, more specifically, to an improved method for depositing an inter-layer dielectric (ILD) on metal lines on semiconductor wafers and in the gaps between adjacent metal lines such that submicron-wide gaps that may have imperfect geometries are completely filled by the ILD according to a chemical vapor deposition (CVD) and medium-pressure sputter etch technique. The above method may find extensive use in the fabrication of multilevel metal semiconductor structures.
2. Description of the Prior Art
There is a constant drive in the processing of semiconductor wafers to increase the density of devices on each die on a semiconductor wafer in order to enhance chip performance and lower manufacturing costs. Increasing the density of devices on each die on a semiconductor wafer enhances chip performance in three ways: first, more complex circuits can be implemented with the additional devices provided by a denser manufacturing technology; second, smaller transistor gates increase device speed; and third, smaller distances between devices decrease the signal propagation delay between devices, thereby improving the speed performance of the chip. Manufacturing costs are lowered because a denser manufacturing technology allows more chips to be produced for each wafer that is manufactured.
As the circuits integrated on semiconductor wafers have become more complex, the interconnecting of the transistors has limited manufacturability. Multilevel metal technology was developed to allow more complex interconnection schemes. Silicon dioxide is typically used as the ILD insulator between multiple metal layers. Multilevel metal technology has an inherent problem that the ILD deposited on the first metal layer must provide a sufficiently planar surface for the next metal layer. As even denser circuits have become desirable, the distances between adjacent metal lines in multilevel metal technology have been pushed into the submicron range. In the submicron range the ability of the ILD to completely fill the gaps between adjacent metal lines becomes a problem. Complete gap filling is necessary to prevent chip failures caused by discontinuities in the ILD between adjacent metal lines.
An ILD deposition process for multilevel metal, submicron metal-gap technology must be selected based on how well it overcomes the problems of gap filling and planarity. Another important consideration is the quality of the ILD as an electrical insulator. Two ILD processes that have been developed for multilevel metal technology are: spin on glass (SOG), and CVD.
SOG was first used in two-level metal technologies with metal line gaps larger than one micron. The limited planarity of SOG and its inability to fill submicron gaps reliably have restricted its use in processes having more than two layers of metal or having submicron metal-gaps. SOG is limited to two-layer metal processes because the SOG surface is not sufficiently planar for additional layers. SOG is not commonly used in submicron metal-gap processes because it does not fill submicron metal-gaps very well. Even when SOG fills a submicron metal-gap, it will usually crack and create reliability problems. Because of the limitations of SOG, other ILD deposition processes have been developed for multilevel metal, submicron metal-gap technology.
An ILD deposited using CVD is often preferred over SOG when ILD quality and multilevel metal capability are considered. CVD deposited ILDs are better, more reliable electrical insulators than SOG. However, CVD deposited ILDs, in general, are even less planar than SOG. This has not limited the use of CVD deposited ILDs because the planarity problem can be solved with an additional planarization process following the gap filling process. Some planarization processes that can be used with CVD ILDs are: photoresist etchback, an additional SOG layer (see U.S. Pat. No. 4,775,550), or chemical-mechanical polishing of the ILD surface (see U.S. Pat. No. 4,944,836). With the additional planarization processing, CVD ILD technology provides a higher quality, more planar ILD than SOG alone.
Two common CVD processes are thermal chemical vapor deposition (TCVD) and plasma enhanced chemical vapor deposition (PECVD). TCVD produces an ILD that fills small gaps, but is low quality because it is porous and contains moisture. PECVD does not fill gaps as well as TCVD, but it provides a high quality, moisture-free oxide. The prior art uses various combinations of TCVD and PECVD in an effort to completely fill small metal-gaps while achieving satisfactory oxide quality.
As the gaps between metal lines shrink to submicron sizes, both TCVD and PECVD exhibit gap filling problems. The prior art improves the gap filling capability of CVD processes by adding etch steps to the CVD ILD deposition process and filling the gap incrementally. Two common etching processes are plasma etching with CF.sub.4 and low-pressure argon sputter etching. Both etching processes etch a CVD deposited ILD layer and widen the upper portion of the gap, thereby allowing a subsequent CVD deposited ILD layer to continue filling the remaining gap. Plasma CF.sub.4 etching is a chemical process whereas argon sputter etching is a physical process. Argon sputter etching is more effective at widening the gap than CF.sub.4 plasma etching.
As shown in FIG. 1, a typical prior art CVD ILD process for submicron metal-gap, multilevel metal technology comprises the steps of: (1) CVD ILD deposition(s) 10, (2) plasma and/or low-pressure sputter etch(s) 12, (3) CVD ILD deposition(s) 14, (4) plasma and/or low-pressure sputter etch(s) 16, and (5) CVD ILD deposition 18. Other typical variations of the prior art ILD deposition process use TCVD combined with PECVD and etching. The prior art process allows gaps as small as 0.8 um, with aspect ratios of 1.0 or less, without reentrant angles, to be reliably filled. However, the prior art process improves gap filling at the expense of lower oxide quality, transistor damage caused by traps and gate-charging, and increased manufacturing costs due to the additional CVD ILD deposition, plasma etch, and low-pressure sputter etch steps.